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general description the max13170e is a three-driver/three-receiver multipro-tocol transceiver that operates from a +5v single supply. the max13170e, along with the max13172e and the max13174e, form a complete software-selectable data terminal equipment (dte) or data communication equip- ment (dce) interface port that supports the v.28 (rs-232), v.10/v.11 (rs-449/v.36, eia-530, eia-530a, x.21), and v.35 protocols. the max13170e transceivers carry the high-speed clock and data signals, while the max13172e carry the control signals. the max13170e can be termi- nated by the max13174e software-selectable resistor termination network or by discrete termination networks. the max13170e has an internal charge pump and a proprietary low-dropout transmitter output stage that allows v.11-, v.28-, and v.35-compliant operation from a +5v single supply. the max13170e features a no- cable mode that reduces supply current to 0.5?, and disables all (high-impedance) transmitter and receiver outputs. short-circuit current limiting and thermal shut- down circuitry protect the receiver and transmitter out- puts against excessive power dissipation. the max13170e has extended esd protection for all the transmitter outputs and receivers inputs. the max13170e is available in a 5.3mm x 10.2mm, 28-pin ssop package and operates over the 0? to +70? commercial temperature range. applications features ? the max13170e/max13172e/max13174e chipsetis a pin-for-pin upgrade to the mxl1544/max3175/ mxl1543/mxl1543b chipset ? supports rs-232, rs-449, eia-530, eia-530a,v.35, v.36, and x.21 ? software-selectable cable termination using themax13174e ? complete dte or dce port with themax13172e/max13174e ? fail-safe receivers ? +5v single-supply operation ? 0.5? no-cable mode ? tuv-certified net1/net2 and tbr1/tbr2-compliant (pending) ? extended esd protection for all the transmitteroutputs and receivers inputs to gnd ?3kv using the human body model?kv using the contact method specified in iec 61000-4-2 ?kv using the air-gap discharge method specified in iec 61000-4-2 max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver ________________________________________________________________ maxim integrated products 1 ordering information 19-3800; rev 0; 5/08 part temp range pin-package m ax13170e c ai+ 0c to + 70c 28 ssop data networkingcsu and dsu data routers pci cardstelecommunications equipment typical operating circuit t1 t2 t3 t4 r1 r2 r3 max13170e rxd rxc txd txc scte t1 t2 t3 r1 r2 r3 max13172e cts dsr rts dtr dcd rxc brxd a (104) rxd b sg (102) shield (101) rts a (105) rts b dtr a (108) dtr b dcd a (107) dcd b dsr a (109) cts a (106) dsr bcts b ll a (141) txd bscte a (113) scte b txc a (114) txc b txd a (103) db-25 connector 13 r4 ll rxc a (115) 18 5 10 8 22 6 23 20 19 4 1 7 16 3 9 17 12 15 11 24 14 2 max13174e + denotes a lead-free package. pin configuration appears at end of data sheet. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v cc = 4.5v to 5.5v, c 3 = c 4 = c 5 = 4.7?, c 1 = c 2 = 1?, t a = t min to t max . typical values are at v cc = 5v, and t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.)supply voltages v cc .......................................................................-0.3v to +6v charge-pump output voltages v dd ....................................................................-0.3v to +7.1v v ee .....................................................................+0.3v to -7.1v v dd to v cc .............................................................-0.6 to +6v logic input voltages m0, m1, m2, dce/ dte , t_in ................................-0.3v to +6v logic output voltages r_out ....................................................-0.3v to (v cc + 0.3v) transmitter outputs t_out_, t3out_/r1in_ (no cable mode or v.28) ..........................................................-15v to +15v short-circuit duration to gnd...............................continuous receiver inputs r_in_t3out_/r1in_ ..........................................-15v to +15v r_ina to r_inb, t3out/r1ina to t3out/r1inb................................................-15v to +15v continuous power dissipation (t a = +70?) 28-pin ssop (derate 9.5mw/? above +70?) ...........762mw junction-to-case thermal resistance ( jc ) (note 1) 28-pin ssop ................................................................25?/w junction-to-ambient thermal resistance ( ja ) (note 1) 28-pin ssop ................................................................67?/w operating temperature range ................................0? to 70? junction temperature .......................................................150? storage temperature range ............................-65? to +150? lead temperature (soldering, 10s) ................................+300? parameter symbol conditions min typ max units v cc operating range v cc 4.5 5.5 v v.11 mode, no load 15 28 v.11 mode, full load 133 180 v.35 mode, no load 21 38 v.35 mode, full load 153 195 v.28 mode, no load 16 30 v.28 mode, full load 29 40 ma v cc supply current (dce mode) (digital inputs = gnd or v cc ) (transmitter outputs static) i cc no cable mode 0.5 10 ? v.11 mode, full load 200 v.35 mode, full load 750 internal power dissipation(dce mode) p d v.28 mode, full load 100 mw v.28, v.35 modes, no load 6.5 6.9 7.1 v.28, v.35 modes, with load, i dd = 10ma 5.6 6.9 v.11 mode 5.15 5.3 5.7 positive charge-pump outputvoltage (note 3) v dd v .11 m od e, v d d var i ati on, i d d = 0m a to 25m a 0.01 v v.28, v.35 modes, no load -6.9 v.28, v.35 modes, with load, i ee = 10ma (note 3) -6.7 -5.4 v.11 mode (note 3) -4.84 -4.5 -4.16 negative charge-pump outputvoltage v ee v .11 m od e, v e e var i ati on, i e e = 0m a to 25m a 0.01 v charge-pump enable time time it takes for both v dd and v ee to reach specified range <1 ms thermal shutdown protection thsd 145 ? note 1: package thermal resistances were obtained using the method described in jesd51-7, using a 4-layer board. for detailedinformation on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver _______________________________________________________________________________________ 3 electrical characteristics (continued)(v cc = 4.5v to 5.5v, c 3 = c 4 = c 5 = 4.7?, c 1 = c 2 = 1?, t a = t min to t max . typical values are at v cc = 5v, and t a = +25?.) (note 2) parameter symbol conditions min typ max units logic inputs (m0, m1, m2, dce/ dte , t1in, t2in, t3in) input high voltage v ih 0.66 x v c c v input low voltage v il 0.33 x v c c v logic-input current i in t1in, t2in, t3in -1 +1 ? pullup resistor r puin m0, m1, m2, dce/ dte to v cc 50 100 170 k logic outputs (r1out, r2out, r3out) output high voltage v oh i source = 4ma 0.66 x v c c v output low voltage v ol i sink = 4ma 0.33 x v c c v output pullup resistor r puy no-cable mode (to v cc ) 71.4 k transmitter output leakagecurrent i z -0.25v < v out < +0.25v, v cc = 0 or no-cable mode +5 0.2 ? v.11 transmitter open-circuit differential outputvoltage v odo open circuit, r = 1.95k , figure 1 -v cc +v cc v r = 50 , figure 1 0.5 x v od o loaded differential outputvoltage (note 4) v odl r = 50 , figure 1 |2| v change in magnitude of outputdifferential voltage ? v od r = 50 , figure 1 0.2 v common-mode output voltage v oc r = 50 , figure 1 3.0 v c hang e i n m ag ni tud e of c om m on- m od e o utp ut v ol tag e ? v oc r = 50 , figure 1 0.2 v short-circuit current i sc v out = gnd 150 ma rise time t r figures 2, 6 4.5 10 ns fall time t f figures 2, 6 6.5 10 ns transmitter input-to-output propdelay t phl , t plh figures 2, 6 16 22 ns data skew |t phl -t plh | figures 2, 6 (note 3) 3 ns output-to-output skew t skewt figures 2, 6 (notes 3, 5) 2.5 ns v.11 receiver differential threshold voltage v th -7v v cm +7v -200 -50 mv input hysteresis ? v th -7v v cm +7v 13 mv receiver input current i in -10v v a,b +10v -0.66 +0.66 ma receiver input resistance r in -10v v a,b +10v 15 30 k rise or fall time t r , t f figures 2, 7 3 ns receiver input-to-output delay t phl , t plh figures 2, 7 23 ns data skew |t phl -t plh | figures 2, 7 ( note 3) 3 ns output-to-output skew t skewr (notes 3, 5) 2.5 ns downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 4 _______________________________________________________________________________________ electrical characteristics (continued)(v cc = 4.5v to 5.5v, c 3 = c 4 = c 5 = 4.7?, c 1 = c 2 = 1?, t a = t min to t max . typical values are at v cc = 5v, and t a = +25?.) (note 2) parameter symbol conditions min typ max units v.35 transmitter differential output voltage v od with load, -4v < v cm < +4v, figure 3 ?.44 ?.55 ?.66 v output high current i oh v a,b = 0 -13 -11 -9 ma output low current i ol v a,b = 0 9 11 13 ma rise or fall time t r , t f figures 3, 6 5 ns transmitter input-to-output delay t plh , t phl figures 3, 6 19 35 ns data skew |t plh - t phl | figures 3, 6, (note 3) 3 ns output-to-output skew t skewt figures 3, 6, (notes 3, 5) 3 ns v.35 receiver differential threshold voltage v th -2v v cm +2v -200 -50 mv input hysteresis ? v th -2v v cm +2v 15 mv receiver input current i in -10v v a,b +10v -0.66 +0.66 ma receiver input resistance r in -10v v a,b +10v 15 30 k rise or fall time t r , t f figures 3, 7 3 ns receiver input-to-output delay t phl , t plh figures 3, 7 (note 3) 23 ns data skew |t phl -t plh | figures 3, 7 (note 3) 3 ns output-to-output skew t skewr (notes 3, 5) 2.5 ns v.28 transmitter open circuit (output high) v dd open circuit (output low) v ee output high 5 6.8 output voltage swing v od r l = 3k output low -6.8 -5 v short-circuit current |i sc | 85 ma output slew rate sr r/f r l = 3k , c l = 2500pf, figures 4, 8 4 30 v/? transmitter input-to-output delayfrom low to high t phl r l = 3k , c l = 2500pf, figures 4, 8 1 2 s transmitter input-to-output delayfrom high to low t plh r l = 3k , c l = 2500pf, figures 4, 8 1 2 s v.28 receiver input threshold low v il 0.8 v input threshold high v ih 2v input hysteresis v hyst 0.25 v input resistance r in -15v v in +15v 3 5 7 k rise or fall time t r , t f figures 5, 9 3 ns receiver input-to-output delay t phl , t plh figures 5, 9 150 ns downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver _______________________________________________________________________________________ 5 electrical characteristics (continued)(v cc = 4.5v to 5.5v, c 3 = c 4 = c 5 = 4.7?, c 1 = c 2 = 1?, t a = t min to t max . typical values are at v cc = 5v, and t a = +25?.) (note 2) parameter symbol conditions min typ max units esd protection (t_out_, t_out_/r_out_, r_in_ to gnd) contact discharge iec61000-4-2 + 8 air-gap discharge iec61000-4-2 ? esd protection human body model ?3 kv note 2: all devices are 100% production tested at t a = +70? and are guaranteed by design for t a = 0? to +70? as specified. note 3: guaranteed by design, not production tested. note 4: v odl is guaranteed at both 0.5 x v odo and |2v|. note 5: ouput-to-output skews are evaluated as a difference of propagation delays between different channels in the same condtionand for the same polarity (lh or hl). v.11 supply current vs. data rate data rate (kbps) 0.1 100 1,000 10,000 1 10 100,000 supply current (ma) 350 0 50 100 150 200 300250 max13170e toc01 dce mode, r = 50 , all transmitters operating at the specified data rate 0 20 6040 80 100 0 100 50 150 200 250 v.28 supply current vs. data rate max13170e toc02 data rate (kbps) supply current (ma) dce mode, all transmittersoperating at the specified data rate, r l = 3k , c l = 2500pf v.35 supply current vs. data rate data rate (kbps) 0.1 100 1,000 10,000 1 10 100,000 supply current (ma) 350 0 50 100 150 200 300250 max13170e toc03 dce mode, fully loaded,all transmitters operating at the specified data rate -5 -2-3 -4 0 -1 43 2 1 5 0 10203040506070 v.11 driver differential output voltage vs. temperature max13170e toc04 temperature ( c) driver differential output voltage (v) dce mode, r = 50 v out+ v out- -10 -4-6 -8 0 -2 86 4 2 10 0 10203040506070 v.28 output voltage vs. temperature max13170e toc05 temperature ( c) output voltage (v) dce mode, r l = 3k v out+ v out- -600 -200-400 200 0 400 600 03 0 4 0 10 20 50 60 70 v.35 output voltage vs. temperature max13170e toc06 temperature ( c) output voltage (mv) dce mode, vcm = 0, full load v oh v ol typical operating characteristics (v cc = +5.0v, c1 = c2 =1?, c3 = c4 = c5 = 4.7?, (figure 10), t a = t min to t max , t a = +25?, unless otherwise noted.) downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v cc = +5.0v, c1= c2 = c4 =1?, c3 = c5 = 4.7? (figure 10), t a = +25?, unless otherwise noted.) 530 535 540 545 550 555 560 -4 -2 -3 -101234 v.35 loaded differential output voltage vs. common-mode voltage max13170e toc07 common-mode voltage (v) differential output voltage (mv) | v od | -500 -300-400 -100-200 100 0 200 400300 500 -10 -6 -4 -2 -8 024 8 61 0 v.11/v.35 receiver input current vs. input voltage max13170e toc08 input voltage (v) input current ( a) dte mode r1in_ r2in_, r3in_ -2.5 -1.5-2.0 -0.5-1.0 0.5 0 1.0 2.01.5 2.5 -10 -6 -4 -2 -8 024 8 61 0 v.28 receiver input current vs. input voltage max13170e toc09 input voltage (v) input current (ma) dte mode v.11 loopback operation max13170e toc10 10ns/div r out t out /r in t in 5v/div 5v/div5v/div r = 50 v.28 loopback operation max13170e toc11 1 s/div r out t out /r in t in 5v/div 5v/div5v/div r l = 3k ,c l = 2500pf v.35 loopback operation max13170e toc12 10ns/div r out t out /r in t in 5v/div 5v/div5v/div full load 0 10 5 2015 3025 35 02 k 1k 3k 4k 5k v.28 slew rate vs. load capacitance max13170e toc13 500 2.5k 1.5k 3.5k 4.5k load capacitance (pf) slew rate (v/ s) r l = 3k sr f sr r downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v cc = +5.0v, c1= c2 = c4 =1?, c3 = c5 = 4.7? (figure 10), t a = +25?, unless otherwise noted.) v oc rr v od figure 1. v.11 dc test circuit 100pf 15pf 100pf 100 r b a b a t figure 2. v.11 ac test circuit v cm 15pf 50 50 125 125 50 50 r b a b a t v od figure 3. v.35 transmitter/receiver test circuit test circuits 0 4 12 8 16 20 02 0 10 30 40 50 60 70 v.11 transmitter propagation delay vs. temperature max13170e toc14 temperature ( c) propagation delay (ns) t phl t plh 0 2 64 8 10 02 0 10 30 40 50 60 70 v.11/v.35 receiver propagation delay vs. temperature max13170e toc15 temperature ( c) propagation delay (ns) t phl t plh 0 10 5 2015 25 30 03 0 4 0 10 20 50 60 70 v.35 transmitter propagation delay vs. temperature max13170e toc16 temperature ( c) propagation delay (ns) t phl t plh downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 8 _______________________________________________________________________________________ v cc /2 90%10% 50% t plh v cc 0 v 0 -v 0 tin_ a - b t r v cc /2 t phl 90% 10% 50% t f f = 1mhz: t r , t f 1ns figure 6. v.11, v.35 transmitter propagation delays +1v -1v v 0h v 0l a -b r 0 inputoutput 0 t plh t phl f = 1mhz: t r , t f 1ns v cc /2 v cc /2 90%10% t r 90% 10% t f figure 7. v.11, v.35 receiver propagation delays 0 t phl 0 v 0 -v 0 tin_ a -3v 3v t f 0 t plh 3v -3v t r sr f = 6/t f sr f = 6/t f t r , t f 10ns v cc /2 v cc /2 v cc figure 8. v.28 transmitter propagation delays timing diagrams c l r l v o a t figure 4. v.28 transmitter test circuit t a r 15pf figure 5. v.28 receiver test circuit test circuits (continued) v ih v il v 0h v 0l a r 1.3v t phl 1.7v t plh t r , t f 10ns v cc /2 v cc /2 90%10% t f 90% 10% t r figure 9. v.28 receiver propagation delays downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver _______________________________________________________________________________________ 9 pin description pin name function 1 c1- v dd charge-pump flying-capacitor negative terminal. connect a 1? ceramic capacitor between c1+ and c1- as close as possible to the device. 2 c1+ v dd charge-pump flying-capacitor positive terminal. connect a 1? ceramic capacitor between c1+ and c1- as close as possible to the device. 3v dd charge-pump positive-supply output. connect a 4.7? ceramic capacitor from v dd to ground as close as possible to the device. 4v cc device supply voltage. bypass v cc with a 4.7? capacitor to ground as close as possible to the device. 5 t1in transmitter 1 logic input 6 t2in transmitter 2 logic input 7 t3in transmitter 3 logic input 8 r1out receiver 1 logic output. internally pull up to v cc . 9 r2out receiver 2 logic output. internally pull up to v cc . 10 r3out receiver 3 logic output. internally pull up to v cc . 11 m0 mode select 0 input. internally pull up to v cc . 12 m1 mode select 1 input. internally pull up to v cc . 13 m2 mode select 2 input. internally pull up to v cc . 14 dce/ dte dce/dte mode-select input. internally pull up to v cc . 15 r3inb receiver 3 noninverting input 16 r3ina receiver 3 inverting input 17 r2inb receiver 2 noninverting input 18 r2ina receiver 2 inverting input 19 t3outb/ r1inb transmitter 3 noninverting output/receiver 1 noninverting input 20 t3outa/ r1ina transmitter 3 inverting output/receiver 1 inverting input 21 t2outb transmitter 2 noninverting output 22 t2outa transmitter 2 inverting output 23 t1outb transmitter 1 noninverting output 24 t1outa transmitter 1 inverting output 25 gnd ground 26 v ee charge-pump negative supply output. connect a 4.7? ceramic capacitor from v ee to ground as close as possible to the device. 27 c2- v ee charge-pump flying-capacitor negative terminal. connect a 1? ceramic capacitor between c2+ and c2- as close as possible to the device. 28 c2+ v ee charge-pump flying-capacitor positive terminal. connect a 1? ceramic capacitor between c2+ and c2- as close as possible to the device. downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 10 ______________________________________________________________________________________ detailed description the max13170e is a three-driver/three-receiver, multi-protocol transceiver that operates from a single +5v supply. the max13170e, along with the max13172e and max13174e, form a complete software-selectable dte or dce interface port that supports the v.28 (rs- 232), v.10/v.11 (rs-449/v.36, eia-530, eia-530a, x.21), and v.35 protocols. the max13170e trans- ceivers carry the high-speed clock and data signals, while the max13172e transceivers carry serial-interface control signaling. the max13170e can be terminated by the max13174e software-selectable resistor termi- nation network or by a discrete termination network. the max13170e features a 0.5? no-cable mode, fail- safe operation, and thermal shutdown circuitry. thermal shutdown protects the drivers against excessive power dissipation. when activated, the thermal shutdown cir- cuitry places the receiver and transmitter outputs into a high-impedance state. mode selection the state of the mode-select inputs m0, m1, and m2determines which serial interface protocol is selected (table 1). the state of the dce/ dte input determines whether the transceiver is configured as a dte or dceserial port. when the dce/ dte input is logic-high, dri- ver t3 is activated and receiver r1 is disabled. whenthe dce/ dte input is logic-low, driver t3 is disabled and receiver r1 is activated (table 1). m0, m1, m2, anddce/ dte are internally pulled up to v cc to ensure a logic-high if left unconnected. no-cable mode the max13170e enters no-cable mode when themode-select inputs are left unconnected or connected high (m0 = m1 = m2 = 1). in this mode, the multiproto- col drivers and receivers are disabled and the supply current drops to 0.5?. the receivers?outputs enter a high-impedance state in no-cable mode, allowing these output lines to be shared with other receivers?outputs, (the receivers?outputs have internal pullup resistors to pull the outputs high if not driven). also, in no-cable mode, the transmitter outputs enter a high-impedance state so that these output lines can be shared with other devices. dual charge-pump voltage converter the max13170e internal power supply consists of a reg-ulated dual charge pump that provides positive and negative output voltages from a +5v supply. the charge pump operates in discontinuous mode. if the output volt- age is less than the regulated voltage, the charge pump is enabled. if the output voltage exceeds the regulated voltage, the charge pump is disabled. each charge pump requires a flying capacitor (c1, c2) and a reser- voir capacitor (c3, c5) to generate the v dd and v ee supplies. figure 10 shows charge-pump connections. max13170e mode name m2 m1 m0 dce/ dte t1 t2 t3 r1 r2 r3 not used ( default v.11 ) 0 0 0 0 v.11 v.11 z v.11 v.11 v.11 rs-530a 0 0 1 0 v.11 v.11 z v.11 v.11 v.11 rs-530 0 1 0 0 v.11 v.11 z v.11 v.11 v.11 x.21 0 1 1 0 v.11 v.11 z v.11 v.11 v.11 v.35 1 0 0 0 v.35 v.35 z v.35 v.35 v.35 rs-449/v.36 1 0 1 0 v.11 v.11 z v.11 v.11 v.11 v.28/rs-232 1 1 0 0 v.28 v.28 z v.28 v.28 v.28 n o c a b l e 1110zzzzzz not used ( default v.11 ) 0 0 0 1 v.11 v.11 v.11 z v.11 v.11 rs-530a 0 0 1 1 v.11 v.11 v.11 z v.11 v.11 rs-530 0 1 0 1 v.11 v.11 v.11 z v.11 v.11 x.21 0 1 1 1 v.11 v.11 v.11 z v.11 v.11 v.35 1 0 0 1 v.35 v.35 v.35 z v.35 v.35 rs-449/v.36 1 0 1 1 v.11 v.11 v.11 z v.11 v.11 v.28/rs-232 1 1 0 1 v.28 v.28 v.28 z v.28 v.28 n o c a b l e 1111zzzzzz table 1. mode selection downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver ______________________________________________________________________________________ 11 fail-safe receivers the max13170e guarantees a logic-high receiver out-put when the receiver inputs are shorted, or when they are connected to a terminated transmission line with all the drivers disabled. this is done by setting the receivers?threshold between -50mv and -200mv in the v.11 and v.35 modes. if the differential receiver input voltage (b - a) is -50mv, r_out is logic-high. if (b - a) is -200mv, r_out is logic-low. in the case of a termi- nated bus with all transmitters disabled, the receiver?differential input voltage is pulled to zero by the termina- tion. with the receiver thresholds of the max13170e, this results in a logic-high with a 50mv minimum noise margin. esd protection as with all maxim devices, a minimum of ?kv-to-gndesd-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. the driver outputs and receiver inputs of the max13170e have extra protection against static electricity. maxim? engineers have devel- oped state-of-the-art structures to protect these pins against esd of ?3kv without damage (hbm). the esd structures withstand high esd in all states: normal operation, shutdown, and powered down. after an esd event, the max13170e keeps working without latchup or damage. esd protection can be tested in various ways. the transmitter outputs and receiver inputs of the max13170e are characterized for protection to the fol- lowing limits: ?3kv using the human body model 8kv using the contact method specified in iec 61000-4-2 5kv using the air-gap discharge method speci- fied in iec 61000-4-2 esd test conditions esd performance depends on a variety of conditions.contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 11a shows the human body model, and figure11b shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest, which is then discharged into the test device through a 1.5k resistor. c2- v ee c2+ max13170e gnd c1- 5v v cc v dd c1+ c1 1 f c54.7 f c21 f c3 4.7 f c4 4.7 f figure 10. charge pump charge-current limit resistor discharge resistance storagecapacitor c s 100pf r c 1m r d 1500 high- voltage dc source device under test figure 11a. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing(not drawn to scale) i r 10% 0 0 amps figure 11b. human body current waveform downloaded from: http:///
iec 61000-4-2 the iec 61000-4-2 standard covers esd testing andperformance of finished equipment. however, it does not specifically refer to integrated circuits. the max13170e help equipment designs to meet iec 61000-4-2, without the need for additional esd-protec- tion components. the major difference between tests done using thehuman body model and iec 61000-4-2 is higher peak current in iec 61000-4-2 because series resistance is lower in the iec 61000-4-2 model. hence, the esd withstand voltage measured to iec 61000-4-2 is gener- ally lower than that measured using the human body model. figure 11c shows the iec 61000-4-2 model, and figure 11d shows the current waveform for the iec 61000-4-2 esd contact discharge test. max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 12 ______________________________________________________________________________________ charge-current limit resistor discharge resistance storagecapacitor c s 150pf r c 50m to 100m r d 330 high- voltage dc source device under test figure 11c. iec 61000-4-2 esd test model t r = 0.7ns to 1ns 30ns 60ns t 100% 90%10% i peak i figure 11d. iec 61000-4-2 esd generator current waveform downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver ______________________________________________________________________________________ 13 cts a 4 2521 18 2 1424 11 15 12 17 93 16 7 1920 23 8 10 6 22 5 13 cts b dsr adsr b dcd adcd b dtr adtr b rts arts b rxd arxd b rxc a rxc b txc atxc b scte ascte b txd atxd b charge pump dte dce rts arts b dtr a dtr b dcd adcd b dsr a dsr b cts a cts b txd atxd b scte a scte b txc atxc b rxc a rxc b rxd a rxd b sg m2 c121 f c13 1 f c54.7 f c21 f c1 1 f c44.7 f c34.7 f 2 21 t1t2 t3 r1r2 r3 2827 26 25 24 23 22 21 20 19 18 17 16 15 3 v cc 5v 12 4 5 6 7 8 9 1011 12 13 14 14 3 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1 5 8111213 c6 100pf c7 100pf c8 100pf m1m0 dce/dte m1m2 dce/dte m0v cc v cc v cc v ee v ee v cc v dd gnd latch max13174e max13170e t1t2 t3 t4 r1r2 r3 26 27 2825 24 23 22 21 20 19 18 17 56 7 8 9 4 3 12 r4 1615 1011 12 13 nc nc 14 m1m2 dce/dte invert m0 db-25 connector max13172e c111 f c10 1 f c9 1 f 1 shield dte_txd/dce_rxd dte_scte/dce_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts m1 dce/dte m0 figure 12. cable-selectable multiprotocol dte/dce port downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 14 ______________________________________________________________________________________ applications information capacitor selection the capacitors used for the charge pumps, as well asfor supply bypassing, should have a low equivalent series resistance (esr) and low temperature coeffi- cient. multilayer ceramic capacitors with an x7r dielec- tric offer the best combination of performance, size, and cost. the flying capacitors (c1, c2) should have a value of 1?, while the reservoir capacitors (c3, c5) and the bypass capacitor (c4) should have a minimum value of 4.7? (figure 10). to reduce the ripple present on the transmitter outputs, capacitors c3, c4, and c5 can be increased. the values of c1 and c2 should not be increased. bypassing for best performance of the charge pumps, connectc3, c4, and c5 closer the device than c1 and c2. cable termination the max13174e software-selectable resistor network isdesigned to be used with the max13170e. the max13174e multiprotocol termination network provides v.11- and v.35-compliant termination, while v.28 receiv- er termination is internal to the max13170e. these cable termination networks provide compatibility with v.11, v.28, and v.35 protocols. using the max13174e termination networks provide the advantage of not hav- ing to build expensive termination networks out of resis- tors and relays, manually changing termination modules, or building custom termination networks. cable-selectable mode a cable-selectable multiprotocol interface is shown infigure 12. the mode control lines m0, m1, and dce/ dte are wired to the db-25 connector. to select the serial interface mode, the appropriate combinationof m0, m1, and dce/ dte are grounded within the cable wiring. the control lines that are not grounded are pulled high by the internal pullups on the max13170e.the serial interface protocol of the max13170e, max13172e, and max13174e is selected based on the cable that is connected to the db-25 interface. v.11 interface as shown in figure 13, the v.11 protocol is a fully bal-anced differential interface. the v.11 driver generates a minimum of ?v between nodes a and b when a 100 (min) resistance is presented at the load. the v.11 receiver is sensitive to ?00mv differential signalsat receiver inputs a?and b? the v.11 receiver rejects common-mode signals developed across the cable (referenced from c to c? of up to ?v, allowing for error-free reception in noisy environments. the receiv- er inputs must comply with the impedance curve shown in figure 14. for high-speed data transmission, the v.11 specifica- tion recommends terminating the cable at the receiver with a 100 resistor. this resistor, although not required, prevents reflections from corrupting transmit-ted data. in figure 15, the max13174e is used to termi- nate the v.11 receiver. internal to the max13174e, s1 is closed and s2 is open to present a 100 minimum differential resistance. the max13170e? internal v.28termination is disabled by opening s3. v.35 interface figure 16 shows a fully-balanced, differential standardv.35 interface. the generator and the load must both present a 100 ?0 differential impedance and a 150 ?5 common-mode impedance as shown by the resistive t networks in figure 15. the v.35 drivergenerates a current output (?1ma, typ) that develops an output voltage of ?50mv across the generator and load termination networks. the v.35 receiver is sensi- tive to ?00mv differential signals at receiver inputs a and b? the v.35 receiver rejects common-mode sig- nals developed across the cable (referenced from c to c? of up to ?v, allowing for error-free reception in noisy environments. 100 min a b c ab c gnd gnd generator balanced interconnecting cable cable termination receiver load figure 13. typical v.11 interface -3.25ma 3.25ma -10v +10v -3v +3v v z i z figure 14. receiver input impedance downloaded from: http:///
max13170e r6 11k r85k r3 124 r252 r152 a b c ab gnd r5 55k 1.4v r7 11k r4 55k max13174e max13170e s3 s1 receiver s2 s1 + - s2 figure 17. v.35 termination and internal resistance networks r6 11k r85k r3 124 r252 r152 a b c ab gnd r5 55k 1.4v r7 11k r4 55k max13174e max13170e s3 s1 receiver s2 s2 + - s1 figure 15. v.11 termination and internal resistance networks 50 50 125 50 50 125 a b c ab c gnd gnd generator balanced interconnecting cable cable termination receiver load figure 16. typical v.35 interface +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver ______________________________________________________________________________________ 15 downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 16 ______________________________________________________________________________________ figure 18. typical v.28 interface a c a c gnd gnd generator unbalanced interconnecting cable cable termination receiver load r6 11k r85k r3 124 r252 r152 a b c ab gnd r5 55k 1.4v r7 11k r4 55k max13174e max13170e s3 s1 receiver s2 s1 + - s2 figure 19. v.28 termination and internal resistance networks in figure 17, the max13174e is used to implement theresistive t network that is needed to properly terminate the v.35 driver and receiver. internal to the max13174e, s1 and s2 are closed to connect the t-network resistors to the circuit. the v.28 termination resistor (internal to the max13170e) is disabled by opening s3 to avoid interference with the t-network impedance. v.28 interface the v.28 interface is an unbalanced single-ended inter-face (figure 18). the v.28 driver generates a minimum of ?v across a 3k load impedance between a?and c? the v.28 receiver has a single-ended input. to aidin rejecting system noise, the max13170e ? v.28 receiver has a typical hysteresis of 0.05v. figure 19 shows the max13174e? terminationnetwork disabled by opening s1 and s2. the max13170e? internal 5k v.28 termination is enabled by closing s3. dte vs. dce operation figure 20 shows a dce or dte controller-selectableinterface. dce/ dte (pin 14) switches the port? mode of operation. see table 1.this application requires only one db-25 connector, but separate cables for dce or dte signal routing. see figure 20 for complete signal routing in dce and dte modes. downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver ______________________________________________________________________________________ 17 cts a 4 2 1424 11 15 12 17 93 16 7 19 20 23 8 10 6 22 5 1318 cts b dsr adsr b dcd adcd b dtr adtr b rts arts b rxd arxd b rxc a rxc b txc atxc b scte ascte b txd atxd b charge pump dte dce rts arts b dtr a dtr b dcd adcd b dsr a dsr b cts a cts b lla lla txd atxd b scte a scte b txc atxc b rxc a rxc b rxd a rxd b sg m2 c121 f c13 1 f c54.7 f c21 f c1 1 f c44.7 f c34.7 f 2 21 t1t2 t3 r1r2 r3 2827 26 25 24 23 22 21 20 19 18 17 16 15 3 v cc 5v 12 4 5 6 7 8 9 1011 12 13 14 14 3 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1 5 8111213 c6 100pf c7 100pf c8 100pf m1m0 dce/dte m1m2 dce/dte m0v cc v cc v ee v ee v cc v dd gnd latch max13174e max13170e t1t2 t3 t4 r1r2 r3 26 27 2825 24 23 22 21 20 19 18 17 56 7 8 9 4 3 12 r4 1615 1011 12 13 14 m1m2 dce/dte invert m0 m1 m2 dce/dte m0 db-25 connector max13172e c111 f c10 1 f c9 1 f 1 shield dte_txd/dce_rxd dte_scte/dce_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts dte_ll/dce_ll figure 20. multiprotocol dce/dte port downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver 18 ______________________________________________________________________________________ t1t2 t3 r3r2 r1 t1t2 t3 d4 txd scte txc rxcrxd ll t4 r4 t4 r3r2 r1 104 104 104 104 104 max13170e max13174e max13174e max13170e t1t2 t3 r3r2 r1 t3t2 t1 rts dtr dcd dsr cts r1r2 r3 max13172e max13172e serial controller txd scte txc rxcrxd rts dtr dcd dsr cts ll serial controller txdscte txc rxc rxd rts dtr dcd dsr cts ll dce dte figure 21. dce-to-dte x.21 interface complete multiprotocol x.21 interface a complete dte-to-dce interface operating in x.21mode is shown in figure 21. the max13170e is used to generate the clock and data signals, and the max13172e generates the control signals and local loopback (ll). the max13174e is used to terminate the clock and data signals to support the v.11 protocol for cable termination. the control signals do not need external termination. compliance testing a european standard en 45001 test report is pendingfor the max13170e/max13172e/max13174e chipset. a copy of the test report will be available from maxim upon completion. downloaded from: http:///
max13170e +5v multiprotocol, 3tx/3rx, software- selectable clock/data transceiver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. 2827 26 25 24 23 22 21 20 19 18 17 16 15 12 3 4 5 6 7 8 9 1011 12 13 14 c2+c2- v ee gndt1outa t1outb r3inb t2outat2outb t3outa/r1ina t3outb/r1inb r2ina r2inb r3ina dce/dte m2 m1 m0 r3out r2out r1out t3in t2in t1in v cc v dd c1+ c1- ssop top view max13170e pin configuration package information for the latest package outline information, go to www.maxim-ic.com/packages . package type package code document no. 28 ssop a28-2 21-0056 chip information transistor count: 2619process: bicmos downloaded from: http:///

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